The new Si5348 clock IC has been announced as the industry's highest performing, most cost-effective packet network synchronizer clock, and has been launched by Silicon Labs. The device combines best-in-class jitter performance with the industry's smallest size and lowest power consumption in a highly integrated, standards-compliant solution. The Si5348 clock enables hardware designers to implement Synchronous Ethernet (SyncE), IEEE 1588v2, and universal frequency translation "on-chip clock tree" solutions for wireless and telecommunications infrastructure, broadband networks such as G.fast. DSL and PON) and data center applications.
SyncE and IEEE 1588 have become increasingly popular methods of providing synchronization over packet networks. With the popularity of these technologies, network equipment designers need more flexible and cost-effective timing solutions, which must be easily integrated into existing hardware architectures. Conventional network synchronizer clocks rely on a strict synchronous clock chip architecture, which draws heavily on traditional Stratum 3 clock ICs, which are not optimized for size, power, or performance.
The Si5348 clock provides a solution that is 50% smaller than traditional synchronizers, reduces power consumption by 35%, and reduces jitter by 80%. These benefits enable hardware designers to simplify the adoption of packet network synchronization without affecting system-level performance. The Si5348 architecture leverages Silicon Labs' proven fourth-generation DSPLL® technology to provide best-in-class jitter performance in timing solutions that are fully compliant with IEEE 1588, SyncE, and Stratum 3 clocking requirements, making the device usable for a variety of timing cards And line card clock architecture. The company said that the Si5348 clock is designed to easily interoperate with IEEE 1588 software running on an external host processor, further simplifying system integration.
"Networks are transitioning from circuit-switched systems to packet-switched systems to improve efficiency, flexibility, and cost-effectiveness, and with the widespread adoption of SyncE and IEEE 1588, equipment manufacturers are looking to minimize the cost and complexity of increasing packet network synchronization Solution. Design, "said James Wilson, director of marketing for Silicon Labs timing products. "Silicon Labs' new Si5348 packet network synchronizer clock provides best-in-class jitter performance, frequency flexibility, power efficiency, and footprint, enabling hardware developers to optimize their designs with on-chip clock tree solutions."
In packet timing applications Medium and high stability oscillators play a vital role in defining the overall performance of the network (in terms of frequency, time, and phase accuracy). The network topology usually determines the type of temperature controlled crystal oscillator (TCXO) or oven controlled crystal oscillator (OCXO) required by each node in the network. The Si5348 clock supports a universal reference input port, enabling the device to be paired with any frequency TCXO / OCXO.
As part of Si5348 product development, Silicon Labs has partnered with Rakon to provide a combined solution that can be used in a variety of SyncE and IEEE 1588 applications. Application ", said Ullas Kumar, Application Marketing Manager, Rakon." By working with Silicon Labs, we provide our customers with a timing solution that can easily optimize frequency, stability, aging and cost at the application level while ensuring compliance with the ITU -T for MTIE and TDEV required standards. "
Si5348 network synchronization clock is preprogrammed at the factory and the number of production samples now available 9mm x 9mm QFN package. The company also offers Si5348-EVB evaluation board, enable developers to quickly complete the configuration from the device in less than five minutes From detailed performance analysis to custom part number generation.
